docs/3d-cgra.pdf
Power grid via stack Lower metal layers, CMOS std. cells
View full datasheet →Parametric NEM/MEM relay design with layout generation (KLayout: GDSII), FEM (Ansys/COMSOL), SPICE models, Liberty models, & more
This repository contains almost everything a researcher might need to get started with NEM relays (MEM relays): (1) a parametric layout generator with KLayout, (2) finite elment models (FEM) with COMSOL/ANSYS, (3) static/dynamic compact model generators with SPICE/Verilog-A (and validation in Mathematica), (4) scripts for characterization with Synopsys SiliconSmart to produce Liberty files for VLSI flows.
A video tutorial of the COMSOL model is available: https://www.youtube.com/watch?v=YCjhU6pspo0
Also, read this paper for more info on potential applications of these models: https://ieeexplore.ieee.org/document/9712515
<img src="figures/mode1comsol.gif" alt="Modal Analysis in COMSOL" width="500"/>The configuration file params.json controls the relay dimensions and model parameters. Descriptions of the parameters are in helper/params_desc.json. contpts.json controls the locations of the contacts. To initialize contact placement to a circle, this file can be deleted.
Please use pip install klayout to install the Python API for KLayout. You can also install the KLayout GUI (https://www.klayout.de/), which may help with layout visualization.
Running cd layouts; python relay.py will generate layouts in DXF, GDSII, and CIF format based on the parameters in params.json. It will also generate comsol/contpts.txt which can be loaded into COMSOL in the next step.
You can also get predictions of the pull-in/pull-out voltages and parasitic capacitances based on the parallel-plate model by running python handcalcs.py. This will use the params specified in params.json to calculate and print these numbers.
SIDE NOTE: when we wanted to use the layout with Virtuoso, we combined layers in KLayout by doing layer operations: layer 6 = layer 6 - layer 7 + layer 8.
To begin, run python comsol_preproc.py to generate params.txt. Then, load the parameters into COMSOL:
Global Definitions/Parameters/Relay Parameters, clear, load from file and select comsol/params.txt.Global Definitions/Parameters/Contact Placement, clear, load from file and select comsol/contpts.txt.NOTE: you may have to slightly modify the parameters once they have been loaded, since COMSOL has a bug where it does not automatically update the relay selections.
The COMSOL model has 5 studies that predict the physics of the multi-pole NEM relay. These are:
Once these have been computed, you can view the results:
You can export the parameters as well for iterative contact placement and SPICE modeling.
For quasi-static sweep, you will have to choose a point on the relay to compute the displacement for. An arbitrary point on any of the contacts should work well.
For iterative contact placement, make sure to run the quasi-static sweep, then choose an operating voltage and displacement contour to extract, then export the displacement contour points. Then, run python contpts.py to get the next set of contacts (modify the parameters internally, if necessary, first). This generates contpts.json, which is used by layouts/relay.py to generate a new layout using the contact placement.
For SPICE modeling, make sure to run python comsol_postproc.py, which generates spice/tech_params.va. These parameters are used by the Verilog-A model.
There is an unfinished ANSYS 2020 Workbench model. It builds the NEM relay geometry using a SpaceClaim script. More work would be needed for this model to accurately predict anything, but it may serve as a good starting point/reference for people trying to model a NEM relay in ANSYS (although COMSOL is better than ANSYS at accurately modeling coupled interactions).
The Verilog-A model is adapted from "Micro-Relay Technology For Energy-Efficient Integrated Circuit" (Hei Kam, Fred Chen) and is designed for use with SPECTRE or HSPICE. It has only been tested with HSPICE 2017.03, but it may also work with other SPICE simulators if simulation settings are adapted correctly.
There are three settings specific to the Verilog-A model in params.json. There is the Q-factor damping Qf, contact resistance Rcont, and air resistance Rair. These should be adjusted before simulation. All parameters are taken from the COMSOL model export: comsol_postproc.py must be run to generate models/tech_params.va that is used to define the simulation parameters.
The first thing to do is generate your Verilog-A model based on the number of bits you want to route with a single relay. You can do this by going into the spice/ directory and running python relay_gen.py {N} where N is the number of bits to route. This will generate the Verilog-A file in the models/ subdirectory called nem_relay_{N}b.va and quasistatic/transient SPICE testbenches in test/ subdirectory. Running these simulations will verify the functionality of the relays by toggling them to see the quasistatic (slow sweep) and transient (fast sweep) response curves. Use cscope and export waveform data to do plots.py plotting.
Next, you can generate one-hot multiplexers from the NEM relays and test these as well. The first step is to run python ohmux_gen.py {N} {M}, where N is the number of bits to route, and M is the number of inputs to the multiplexer. This will generate several files: a SPICE model for the multiplexer without buffering (models/nem_ohmux_{M}i_{N}b.sp), a SPICE model for the multiplexer with an inverter to buffer the signal (models/nem_ohmux_invd{D}_{M}i_{N}b.sp), testbenches for both of these (test/ohmux_test_{M}i_{N}b.sp, test/ohmux_test_invd{D}_{M}i_{N}b.sp), and finally an instance file (liberty/control/nem_ohmux_invd{D}_{M}i_{N}b.inst) that can be used to characterize the SPICE model with SiliconSmart. By default, the inverter is taken from TSMC40 library through tsmc40inc.sp; using a different inverter is a matter of swapping out the implementation. The inverter drive strength can be specified through a command-line option e.g. python ohmux_gen.py 1 2 -D1 will create a D1 inverter, and the area of a signle inverter can optionally be specified with --area option. The inverter area will be automatically multiplied by the number of bits to get the total area.
TODO: non-one-hot multiplexers
The Liberty model generation has been tested with SiliconSmart M-2017.03-2. Library Compiler (LC) also needs to be loaded to compile the Liberty (.lib) files to DB (.db) files. In order to use SiliconSmart, first create the SPICE models in the previous step. Then simply run siliconsmart run.tcl to run the characterization flow. This will generate the library with all the .libs and .dbs necessary for a standard EDA flow. To debug, see the SPICE simulations for the different characterizations.
Running the Mathematica notebook will solve the damped ODE model of the NEM relay and yield the transient displacement curve. It is good for validating the effect of Q-factor damping.
Imported into the CommunityCAD Archive with attribution preserved. All rights remain with the original author under the stated license.
docs/3d-cgra.pdf
Power grid via stack Lower metal layers, CMOS std. cells
View full datasheet →docs/area-1.pdf
Area (um?) PE Tile CMOS Area 14000 12000 10000 8000 8029.0 6000 4000 2000 NEMS CMOS
View full datasheet →docs/area-breakdown.pdf
CMOS PE Core Average PE Area Breakdown by Module Other PE Core CBs NEMS 54.3% 60.8% SB SB Other
View full datasheet →docs/area-utilization-2.pdf
oa
View full datasheet →docs/area-utilization-3.pdf
Plate Area To Total — — Area
View full datasheet →docs/area.pdf
Total Area (um2) 1/.3% reduction Module i CBs {i Other ff PE Core mss
View full datasheet →docs/cgra-comps.pdf
4 3,2. 1.0 4) 3| 2) 1| 0 be ctl oO VIE}CI|LIO O'L'icle'p OlLCeED 0123 4 (b)
View full datasheet →docs/cgra.pdf
Lu [ae — ~ Cc i) € wv Lu jo) Cc n n oO O ie) = fa (SB) Switch box Connection box (CB)
View full datasheet →docs/cpump-tran.pdf
Voltage (V) — V(in): buffered 2.5V clock —24 — V(out): NEM relay body bias ---- 95% of V(out) steady state 10-4 -10-3,——«10-2.—«10-2 10° 10! Time (us)
View full datasheet →docs/delay-1.pdf
Slack (ps) Slack on Crit. Path ££ Oo 1 Ww oOo L N oO L BR Oo L 53 52 CMOS NEMS
View full datasheet →docs/disp-sweep.pdf
(a) 40 — FEM 30} __ spice E 50. ---- Vp; hand N ---- Vp, hand 104 pe 0 1 0 1 2 3 4 5 Ves (V) (b) 40 307 Ss £ 20 ; N SPICE sim 104 —— Vege = 5V Q=0.5 0
View full datasheet →docs/iterative-contact-placement.pdf
Std. of Reont (Q) a ON ON FD ~40x reduction in std(R.ont) by i=3 1 2 3 Placement Iteration = a Nu Std. of Foont (NN) - © oO
View full datasheet →docs/layout-2.pdf
3.78um Anchor sharing
View full datasheet →docs/layout-5.pdf
nm 35 30 25 20 15 10
View full datasheet →docs/mux-energy-labeled.pdf
Switching Energy (a.u.) 10° Mux IZ Switching Energy -@-2i18b CMOS —%*—2i 8b NEMS -e-4i18b CMOS —*—4i 8b NEMS -e-10i 85 CMOS —*-10i 8b NEMS 2 ee ~~ ----«-- 10° 101 Load Capacitance (fF)
View full datasheet →docs/mux-feol-area.pdf
FEOL Area (a.u.) 5.76x lower N 7.5x lower 27.7x lower Ne » f is 2-input 8b 4-input 8b 10-input 8b Mux Mux Mux mCMOS m NEMS
View full datasheet →docs/nem-mux-3.pdf
NEM Relay Implementation ' Example Signals: | | Red= =Hi, Black=Lo ' Relays: : Green=ON state | Gray= OFF state eee es CMOS INV buffer (x8, for 8b signal)
View full datasheet →docs/nems-mux-3.pdf
Via Stacks b/w Relays and CMOS Channels Inter-Relay ' + Inverters (x8, for 8bits) Signal Lines ioe CMOS Layer
View full datasheet →docs/power-breakdown.pdf
CMOS SB Average PE Power Breakdown by Module CBs % PE Core 16.1% NEMS Other SB CBs PE Core Other
View full datasheet →docs/power-compiler-ds.pdf
Datasheet SYNOPSYS" Accelerating Innovation Power Compiler Power Optimization in Design Compiler Overview Power Compiler™ automatically minimizes power consumption at the RTL and gate level, and enables concurrent timing, area, power and test optimizations within the Design Compiler® synthesis…
View full datasheet →docs/power.pdf
2 80 S ~~ 60 3 5 40 a B20 ° FOP nw 2 i 5 2 Conv 3x3 Cascade Module i CBs § Other ll PE Core ™@ sB
View full datasheet →docs/quasistatic-curve-labeled.pdf
Relay z-Disp. (nm) 40 30; 207 10; — FEM — SPICE ---- Vp; analytical ---- Vpo analytical | Hysteresis oo OFF 1 2 3 4 5 Gate-to-Body Voltage Vgep (V)
View full datasheet →docs/relay-side-view-cartoon.pdf
(a) Electrostatic Force OFF state Body (B) Dielectric Spacer Channel (b) Current Flow ON state Body (B) Dielectric Spacer Channel Source (S) Drairi (D) Anchor Hysteresis ~ TE V Vo Vhold Vi GB
View full datasheet →docs/relay-side-view-mp-cartoon.pdf
Dielectric Spacer Channel Channel sil) G |p1\)c{s2) a | pz
View full datasheet →docs/sweeps.pdf
— FEM 30) —— SPICE a . i I E 50 Voi analytical N Vpo analytical H I SPICE sim
View full datasheet →docs/area-2.pdf
PE Tile Area Breakdown Other PE Core CBs CMOS PE Core NEMS
View full datasheet →docs/area-utilization.pdf
+40% ; Plate area util. Area = rT ™ Total — — Area Area utilization: 0.33 Area utilization: 0.54
View full datasheet →docs/cgra-design-flow.pdf
NEMS Based Standard Cell Modeling Flow NEM Relay Layout Generation (KLayout) Finite Element Modeling (COMSOL) Extracted Parameters Liberty Model Generation Parasitics NEM Relay Based Multiplexer (Standard Cell) Layout (Virtuoso) CGRA Logical Design Flow CGRA Generation (Genesis2) Synthesis (Design…
View full datasheet →docs/contact-placement-results.pdf
Low contact force High contact force ~Equal contact forces Circular \ a Oo o a a a a o a o QO o a a o Qo o a o o a a o o Oo Qo Oo Oo O Iteration 1 Iteration 2 Iteration 3
View full datasheet →docs/contact-variation.pdf
(Nu) "4 yo uoljelAag paepueys (Co) N dad od Oo t O ioe) c| toa) o> 3 2 3/= Tw 9 Pax “ > 6 oa +2 t% a ° (u) 1U0> 54 jo uoljelAog psepueys Placement Iteration
View full datasheet →docs/delay-2.pdf
CMOS NEMS PE Tile Delay Breakdown 1/0 SB CB PE Core 87.3% 0.7% 10.1% 1.9% 1.6%
View full datasheet →docs/delay.pdf
Module mce PE Core ™ sB yo + N (su) Aejaq yie. SWAN SOWD ° 'd
View full datasheet →docs/design-flow.pdf
NEMS Cell-Level Modeling Flow Relay Layout (KLayout) GDS FEM (COMSOL) ICP Params \GDS SPICE Model NEMS Stdcells (HSPICE) (Virtuoso) Liberty Model (SiliconSmart) CGRA Generator (Genesis2) CGRA Digital Design Flow App Suite (Halide) RTL Bitstream Testbench RTL RTL Simulation (Verilator) VCD Waveform…
View full datasheet →docs/icp.pdf
Initialize contact placement Run FEM analysis Expected Roont variation below spec threshold? YES Extract valid disp. contour at VY, Find contour’s connected components Place contacts at chosen distances from closest point to origin of each connected component Connected Components
View full datasheet →docs/layout-1.pdf
Anchor Electrostatic Plate SI. & Anchor Channel as SEN Contact Beam——> [Ps ee Body NS Release Holes [SS] BEOL Metal i“) BEOL Metal Spacer Ss) BEOL Landing Pads Contact “ Pair & RSS Channel Release Holes
View full datasheet →docs/mux-delay.pdf
Delay (ps) T T 10° 10? Load Capacitance (fF) Mux I>Z Delay -e- ttttt tte 2i 8b CMOS 4i 8b CMOS 10i 8b CMOS 2i 8b NEMS (Ros = 80Q) 4i 8b NEMS (Ros = 80Q) 101 8b NEMS (Ros = 80Q) 2i 8b NEMS (Ros = 5kQ) 4i 8b NEMS (Ros = 5kQ) 10i 8b NEMS (Ros = 5kQ)
View full datasheet →docs/mux-energy.pdf
Switching Energy (a.u.) 10° 4 10-1 4 Mux I>Z Switching Energy -e-2i18b CMOS —%®2i 8b NEMS =e-4i18b CMOS —*—4i 8b NEMS -e-10i 8b CMOS —*-10i 8b NEMS Load Capacitance (fF)
View full datasheet →docs/nem-mux-1.pdf
Input Bits ' Example Signals: — | Red= =Hi, Black=Lo : Relays: : Green=ON state | | Gray= OFF state | -------- Relay passes NEM Relay One-Hot ; Z signal 2 Mfough to Output Bits Mux (8-bit) pin
View full datasheet →docs/nem-mux-2.pdf
NEM Relay Implementation ------- I l a) ! oT LQ: l a4 oO ' 1Do BB! 'gQ = ' ' a Zu, i(@ - ,Ouw! ;azt wo ll O; ae nT ac il! ‘eo 8&0 >, ' © 0 1s DO Or x} ; WW Oo woo: So Relay passes signal |, through to Z
View full datasheet →docs/nem-mux-internals.pdf
sig indu| Selection Bits (One-Hot) SS SS ° = + > = Oo Ss ? = io} tad Ss c ct, cs iv) x ic) s N Zz S}ig }ndjno NEM Relay Implementation | Example Signals: | Red= Hi, Black=Lio CMOS INV buffer (x8, for 8b signal)
View full datasheet →docs/parasitic-caps.pdf
Capacitance C,,: Capacitance C,,: Body p Dielectric S OFF: Bact Air/Vacuum ON: t Perimeter = P, Leo Source/Drain Le Terminal Substrate tl Dielectric Capacitance C,,: 7 D
View full datasheet →docs/power-plot.pdf
Cascade Conv 3x3 Harris Module @ CBs @ Other ff PE Core i ss ane CMOS NEMS CMOS -— NEMS —
View full datasheet →docs/power_plot.pdf
Average Power by Module (mW) Cascade StI Conv. 1x2 (i! Conv. 2x1 (is Mmm PE Core C 3x1 (mm Other . 1 is onv. 2x mE CBs Cony. 3X3 i | mm SB Harris [ss 0.0 0.2 0.4 0.6 Average Power (mW)
View full datasheet →docs/ppa-benefits.pdf
nN 1% 4 mw Overall oan 5ns_ 5ns m= Other m CBs m SBs mw PE Core a 7675 CMOS NEMS CMOS NEMS CMOS NEMS Area (ym?) Clock Period (ns) Power (mW)
View full datasheet →docs/quasistatic-curve.pdf
Relay z-Disp. (nm) S ro) WwW Oo fl N Oo 1 pay oO 1 Oo Oo —— FEM ---- Vpj analytical ---- Vpo analytical 1 2 3 4 Gate-to-Body Voltage Veg (V)
View full datasheet →docs/relay-layout.pdf
(a) Anchor Beam -— Anchor Channel Contact Body Release Holes BEOL Metal Contact > jn 7 BEOL Metal Spacer Pair& ~~ S BEOL Landing Pads Channel Release Holes Anchor sharing (b) © 3.78um
View full datasheet →docs/spice-model.pdf
Mechanical Model (Contact force is modeled but not shown) Spring (k) Damper (c) Electrical Model
View full datasheet →docs/transient-curve-fall.pdf
S ro) WwW Oo pay oO z Displacement (nm) NJ (o) Oo 0 200 400 600 Time (us) SPICE sim Vos = 5.0V Q=0.5 800 1000
View full datasheet →docs/transient-curve-rise-labeled.pdf
Relay z-Disp. (nm) SPICE sim 107 — Veg, = 5.0V Q=0.5 OFF-state (0) T T T T T 00 O05 10 315 2.0 2.5 3.0 Time (us)
View full datasheet →docs/transient-curve-rise.pdf
Relay z-Disp. (nm) SPICE sim 0 00 O05 10 15 2.0 2.5 3.0 Time (us)
View full datasheet →