NEMS Cell-Level Modeling Flow
Relay Layout (KLayout)
GDS FEM (COMSOL) ICP
Params \GDS
SPICE Model NEMS Stdcells (HSPICE) (Virtuoso)
Liberty Model (SiliconSmart)
CGRA Generator (Genesis2)
CGRA Digital Design Flow
App Suite (Halide)
RTL Bitstream Testbench
RTL RTL Simulation (Verilator)
VCD Waveform
Power/Delay Estimation
Gate-Level Simulation
(DesignCompiler) (VCS)
Switching Behavior
Place-and-Route Power Estimation
(PTPX)