CiPc
Supersedes:
IPC-2221A - May 2003 IPC-2221 - February 1998
IPC-2221B
Generic Standard on Printed Board Design
Developed by the IPC-2221 Task Group (D-31b) of the Rigid Printed Board Committee (D-30) of IPC
Users of this publication are encouraged to participate in the development of future revisions.
Contact:
IPC
3000 Lakeside Drive, Suite 309S Bannockburn, Illinois 60015-1249
Tel 847 615.7100
Fax 847 615.7105
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November 2012 IPC-2221B Table of Contents 1 4 = MATERIALS ou. eects ceeeeeeeeeeeeee 21 1d : 4.1 Material Selection ........ccccccceeeeseeseeneeeeeees 21 1.2 Documentation Hierarchy 1 4.1.1 Material Selection for Structural Strength 1.3 Presentation al 4.1.2 Material Selection for Electrical Properties .... 21 1.3.1 Dimensional Units ........ccceceeeeeeeseseeneeeneees 1 4.1.3 Material Selection for Environmental 14 Interpretation 1 PLOPerties oo. ees ces eeeeseeeeeteeseeeseeeseees 21 15 Definition of Terms 2 42 Dielectric Base Materials (Including : Oo ~ ~ Prepregs and Adhesives) ........:essescesseestesteeeeeees 21 1.5.1 IY, O0s 0) 12 F: 2 . . 4.2.1 Preimpregnated Bonding Layer (Prepreg) ....... 22 1.6 Classification of Products .......ccccccccecceeeeeeeeeee 2 . 161 Printed Board T 4.2.2 Adhesives 6. te 162 pest ee oan Cl -_ : 4.2.3. Adhesive Films or Sheets . 163 mrodcibiie L net cation 5 4.2.4 Electrically Conductive Adhesives «0.0.0.0... 24 6. ty Level oo. eee eeeeeeeeeeees ro en my eve 4.2.5 Thermally Conductive/Electrically 17 Revision Level Changes ....ssssssssssssssssssssseeeeeeeeeee 3 Insulating Adhesives ......c.ccecseessesseseeseestesteeseeees 24 2 APPLICABLE DOCUMENTS. ........ccccccccccscecesescecesesees 3 43 Laminate Materials... ccc 25 2.1 TPC ceeceessecsseesssesssesssecssecssecssecssecesecssecsseesuecssecssecese 3 4.3.1 High T, Laminates ..... 2.2 Joint Industry Standards ......0000... 4.3.2 Color Pigmentation 23 Society of Automotive Engineers . 4.3.3 Dielectric Thickness/Spacing «0.0.0.0... 25 24 American Society for Testing and Materials ..... 5 4.3.4 Thermally Conductive Laminates «0.0.0.0... 25 25 Underwriters Labs 4.3.5 | Minimum Base Material Thickness for 26 IEEE. . PC Card Form Factors : 27 ANSI . . 44 Conductive Materials ” 26 2.8 ANSI/ESD oisecescsscscscces ses esestesesseseeseesessesesseseeseens 5 44.1 Electroless Copper Plating 2.9 PCMCIA. ooeceececececccceceseeseseeseesessesneatssessssesneseeseene 5 4.4.2 Semiconductive Coatings srr 29 4.4.3 Electrolytic Copper Plating 0... cee 29 3 GENERAL REQUIREMENTS seeeeseeeeeeeeseesseseeeeeeeeass 6 4.44 Gold Plating 7 3.1 Information Hierarchy . 4.4.5 Immersion Silver . 31 3.1.1 Order of Precedence . . . 4.4.6 Immersion Tin wen 3.1.2 End-Product Performance Requirements ; i . i . . 4.4.7 Organic Solderability Preservative (OSP) ....... 32 3.2 Design Considerations ........ccceeeeeeeeneeeeeeeee 8 . . . oo, 4.4.8 Nickel Plating o...cccccceceeeeeeeeseeneteeeeeeeenees 32 3.3 Schematic/Logic Diagram .. + 449 +n/Lead Plat 3.4 Density Evaluation id a Tin/Lead P ating . 3.5 Parts List sscscsssstatseietetscisetetetsetenntneset o 44:10 Solder Coating ...... 3.6 Test Requirement Considerations «0.0.0.0... 0 44.11 Other Metallic Coatings for Edge Printed : Board Contacts 3.6.1 Electrical “ 44.12 Metallic Foil/Film ... ae Printed Board Assembly Testability 4.5 Electronic Component Materials .............000+ 36 ~ Boundary Scan Testing swcwrwcrwnenerrenee 3 4.5.1 | Embedded (Buried) Resistors ........:::csseseeee 36 3.6.4 Functional Test Concern for Printed Board 452 . . ASSEMDI]iCS o....seececces tees teseeseeeseesesneseeseeneseseeneeee 4 a Embedded (Buried) Capacitors ... 3.6.5 In-Circuit Test Concerns for Printed Board 4.5.3 Embedded (Buried Inductors) . ASSEMDIiCS oo. eeeeceeeeeseseseeeeteeseseeseeseeeeeseeeseaeeneees 5 4.6 Organic Protective Coatings ..... we 3.6.6 Mechanical ......cccccecceseeeeseesesneteeeeeeeseesesneneees 7 4.6.1 Solder Mask Coatings .....cccceeeeseeseeseeeeeesees 36 3.7 Layout Evaluation... 7 4.6.2 Conformal Coatings ..0...ccccceeeeeseseseeteeeeeenees 37 3.7.1 Printed Board Layout Design ... 4.6.3. Tarnish Protective Coatings . 3.7.2. Feasibility Density Evaluation .. 47 Marking and Legends
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IPC-2221B
November 2012
4.7.1
5
5.1 5.1.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6
5.2.7 5.3
5.3.1 5.3.2 5.3.3 5.3.4
5.4 5.4.1 5.4.2 5.4.3 5.5 5.6 5.7
6
6.1 6.1.1 6.1.2 6.1.3 6.2 6.3 6.3.1 6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
ESD Considerations ... MECHANICAL/PHYSICAL PROPERTIES ............. 39 Fabrication Considerations ......... . 39 Bare Printed Board Fabrication . Product/Printed Board Configuration . 39 Printed Board Type ........cccceeeeeseeeeeeeneeeeees 40 Printed Board Size wo... eeeeeeeeeeeeeeeeees 40 Printed Board Geometries (Size and Shape) ... 42 Bow and Twist .... Structural Strength Composite (Constraining-Core) Printed Boards .... Vibration Design . Assembly Requirements 0.0.0... 44 Mechanical Hardware Attachment .....0.000000 44 Part SUpport oo... eeeseseeeeteteeeneneeeeees 44 Assembly and Test .....cccceeceeseeeeeneeeeeeees 45 Tooling Rails for PC Card Form Factor Printed Boards oo... eeeeeeseeeeeneeeeseees 45 Dimensioning Systems .........cceeeeeeeeeeeeees 45 Dimensions and Tolerances ..........cceeeeeee 45 Component and Feature Location . 45 Datum Features 46 Printed Board Thickness Tolerance . 49 Panelization oo... eeeeeeeeeseeeseeeeeeteneneeeeees 49 Palletization oo. eeseeeeeneteteneeeneeees 49 ELECTRICAL PROPERTIES .. . 53 Electrical Considerations 53 Electrical Performance . 53 Power Distribution Considerations ..........0... 53 Circuit Type Considerations... 53 Conductive Material Requirements «00.0.0... 56 Electrical Clearance oo... eeeeeeeeeeneeeeees 56 Bl-Internal Conductors wo... 57 B2-External Conductors, Uncoated, Sea Level to 3050 m [10,007 feet] 0.0... 57 B3-External Conductors, Uncoated, Over 3050 m [10,007 feet] oo. eeeeeseeeeeeneteeeeeeee 57 B4-External Conductors, with Permanent Polymer Coating (Any Elevation) «0.0.0.0... 58 A5-External Conductors, with Conformal Coating over Assembly (Any Elevation) ......... 58 A6-External Component Lead/Termination, Uncoated, Sea Level to 3050 m [10,007 feet] oe eeecceeseeseeeeeeseseeteseeesteneneeees 58 A7-External Component Lead/Termination, with Conformal Coating (Any Elevation) ....... 58
6.4 Impedance Controls 6.4.1 Microstrip . 6.4.2 Embedded Microstrip oo... 60 6.4.3 Stripline Properties oo... eee 61 6.4.4 Asymmetric Stripline Properties 6.4.5 Capacitance Considerations .. 6.4.6 Inductance Considerations .... 7 THERMAL MANAGEMENT .........0000.00. 65 7A Cooling Mechanisms 7.1.1 Conduction TAQ — Radiation cece eeeeeessseseeeeeseseenenseeeees TAB COmVvection oo... eeeessseseseeeseseeneeeeeees 66 TA4 — Altitude Effects 0... cceeeseeeeseseeneeeeeees 66 7.2 Heat Dissipation Considerations 7.2.1 Printed Board Housings ... 7.2.2 Individual Component Heat Dissipation .. 7.2.3. Thermal Management Considerations for Printed Board Heatsinks .........cccceeceseeeeeeees 67 7.2.4 Assembly of Heatsinks to Printed Boards ....... 68 7.2.5 Special Design Considerations for SMT Printed Board Heatsinks .........cccceeceseeeeeeees 69 7.3 Heat Transfer Techniques «0.0.0.0... cee 70 73.1 Coefficient of Thermal Expansion (CTE) Characteristics ......ccceeceesesessesessseeeeeseseeeeneees 70 7.3.2 Thermal Transfer ........cccccecssseseeeeseseeeeneeeeees 70 7.3.3 Thermal Matching 0... eee 70 TA Thermal Design Reliability 0.00 70 8 COMPONENT AND ASSEMBLY ISSUES .............. 72 8. General Placement Requirements «0.0.0.0... 73 8.1.1 | Automatic Assembly 8.1.2. Component Placement 8.1.3. Orientation 8.1.4 — Accessibility 0. eseteeeeeneeeeseeeeeeees 8.1.5 Design Envelope oo... ceeeseeeeeeeeeeeeseeeeeeeee 8.1.6 Component Body Centering 8.1.7. Flush Mounting Over Conductive Areas . 8.1.8 Clearances 8.1.9 Physical Support ......c.eeeccseseeseeseeeeeeeeeneeeees 76 8.1.10 Heat Dissipation 0... ceeeeseseeseseeeeeeteeeeteneees 78 8.1.11 Stress Relief ccc cecceceeeeesesteeeeeeeeeeeeeeneneees 78 8.2 General Attachment Requirements .................. 79 8.2.1. Through-Hole .... 8.2.2 Surface Mounting 8.2.3. Mixed Assemblies .. 8.2.4 Soldering Considerations 00.0... cece 80 8.2.5. Connectors and Interconnects 0... 81
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November 2012 IPC-2221B 8.2.6 Fastening Hardware occ eeeeeeeteeeeees 83 10 GENERAL CIRCUIT FEATURE 8.2.7 StHMMELS cscssssnsentnsentnsevtntnseneeeee 83 REQUIREMENTS nso cvrereretcrrctcncatctcn 02 82.8 Lands for Flattened Round Leads . 84 0.1 Conductor Characteristics seseseseeeseseseeusesseeeees 02 8.2.9 Solder Terminals 0.1.1 Conductor Width and Thickness . 02 8.2.10 BYelets sesesossssssntntsesetnsstisntnnntisetanntneee go -:10-1.2_ Electrical Clearance 05 8.2.11 Special Wiring ....scssccssccssssssssssessssseesseseeeesseee 86 0.1.3 Conductor ROULNE vere rnteecntetenreteten 05 8.2.12 Heat Shrinkable Devices . 37 0.1.4 Conductor Spacing coseeeeeeeeseseseeseseseeeeseaseeaeeees 10s) 82.13 Bus Bar 37 0.1.5 Plating Thieves a 06 8.2.14 Flexible Cable o.escssssssosenssinsnnenisiannneeien 87 0.2. Land Characteristics 06 83 Through-Hole Requirements ...... 37 0.2.1 Manufacturing Allowances seseseesacseseeseeeeeeeeeees 06 8.3. Leads Mounted in Through-Holes ... . 0.2.2 Lands for Surface Mounting 06 8.4 Standard Surface Mount Requirements O91 0.2.3 Test Points _ 06 8.4. Surface-Mounted Leaded Components ............ 91 0.2.4 Orientation Symbols _ 06 8.4.2 Flat-Pack Components ........ 0.3 Large Conductive Areas oo... 06 8.4.3. Ribbon Lead Termination 11. DOCUMENTATION ...000.. ccc eeeeeeee 06 8.4.4 Round Lead Termination .... al Special Tooling 0. eeeeeeeseneeseeeeeeeee 08 8.4.5 Component Lead Sockets .......::secsceeseeeteeeeees 2 Layout .... 08 8.5 Fine Pitch SMT (Peripherals) ... 2.1 Viewing .. 08 8.6 Bare Die . 2.2 Accuracy and Scale 08 8.6.1 Wire Bond ooeeceeeccceesesecseseeseesestesecsecteseeneetenteneene 93 2.3 Layout NOtes ...cccccsecessesessesteseesescesnesesteseeneens 08 8.6.2 Flip Chip .2.4 Automated-Layout Techniques . 08 8.6.3. Chip Scale 3 Deviation Requirements .... 08 8.7 Tape Automated Bonding ... A Phototool Considerations ... 09 8.8 Grid Array SMT oo. esseteseeeeeeeeeseeneees 4.1 Artwork Master Files .......cccceceeseeeeeeeee 09 8.9 No-Lead Devices .....c.csceecesseeseeseeseseesesesesteneees 94 4.2 Film Base Material... ccceseeseeeeeeeeeeeee 09 8.9.1 | Small Outline and Quad Flat No Lead with 4.3. Solder Mask Coating Phototools «0.0.0... 09 Pullback Leads (PQFN, PSON) .... 8.10 Compliant Pin Design Guidelines .... 12 QUALITY ASSURANCE uw... ee 09 2.1 Conformance Test Coupons . 09 9 HOLES/INTERCONNECTIONS .........0000 ce 95 22 Material Quality Assurance 10 9.1 General Requirements for Lands with Holes .. 95 . 2.2.1 Laminates 10 9A Land Requirements ..........cccc ee eeeeeeseneeeeeee . . . . 2.2.2 Compliant Pin wo. ceeeeceeeeeseeseeeeteeeeeeeeneees 10 9.1.2 Annular Ring Requirements «0.0.00. . a 2.3 Conformance Evaluations ..........cc.ccccccceeeees 10 9.1.3 Thermal Relief in Conductor Planes 231 C . 4 Locati 10 9.1.4 Lands for Flattened Round Leads . 339 oupon Quantity an ocation 9.2 Holes ooeeeeseecesceseeeseesseseeeeteseeeeeseees 3.2 Coupon Identification 7 I4 9.2.1 Unsupported Holes .....ccccceeeeceeseeeesesesneneeeees 23.3 General Coupon Requirements l4 9.2.2 Plated Holes 2.4 Individual Coupon Designo... 14 9.23 Location 2.4.1 Plated Hole Evaluation (Thermal Stress, 924 1 _ Rework Simulation, Registration) Coupons .. 114 2. Hole Pattern Variation 20.0... 24.2 Moisture and Insulation Resistance 9.2.5 Location Tolerances 1.0.0... 00 COUPONS oeieeeeeeeceeteseseeteseseeeeneneseeeeeeneeeseseeneeeee 15 9.2.6 Quantity ol 2.4.3 Hole Solderability Coupons .......:::sssssssssssesee 15 9.2.7 Spacing of Adjacent Holes ol 2.4.4 Surface Mount Solderability Coupons ........... 15 9.2.8 Aspect Ratio cece eeeeteeeneneeeeeeees Ol 2.4.5 Interconnect Resistance and Continuity 9.3 Via Protection wc. ccccececeseeeeseesesseteeeseeeeeeeeees Ol COUPONS ooeeeececeeeececseeeeeseseeesesteeeeeeeetseseeeneees 15 9.3.1 Via Protection Requirements .. Ol 2.4.6 Solder Mask Adhesion Coupons ........... 15 9.3.2 Ol 2.4.7 Surface Insulation Resistance Coupons 15
vii
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IPC-2221B
November 2012
12.4.8
12.4.9
12.4.10 Optional Legacy Registration Coupons
12.4.11 Legacy N Coupon (Peel Strength, Surface Mount Bond Strength - Optional for SMT) .. 116
12.4.12 Coupon X (Bending Flexibility and
Controlled Impedance Coupons
Peel Strength and Plating Adhesion COUPONS oo. cece eeeeeseeeeteeeeeteneeseeeeee 116
Endurance, Flexible Printed Board) ............... 116 12.4.13 Process Control Test Coupon... 116 APPENDIX A oeeeeceeccceceeeseeeeeeeeeeseeeeeeeseseseneeneeees 117 APPENDIX Bo ooeeeecececceccceeseteeeteeeeseeeeeetseseseaeaeaeaes 142 APPENDIX Cooooeeecececcccceecseteeeeeeeeeeeeeeetseseeeaeaeaeees 162 Figures Figure 1-1 Microvia Definition ... Figure 3-1 Package Size and I/O Count Figure 3-2 Test Land Free Area for Parts and Other Intrusions . 16 Figure 3-3 Test Land Free Area for Tall Parts 16 Figure 3-4 Probing Test Lands . 16 Figure 3-5 Example of Usable Area Calculation, mm [in] (Usable area determination includes clearance allowance for edge printed board connector area, printed board guides, and printed board extractor.) 18 Figure 3-6 Printed Board Density Evaluation . 20 Figure 4-1 HASL Surface Topology Comparison Figure 5-1 Example of Printed Board Size Standardization, mm [in]... ee 4 Figure 5-2 Typical Asymmetrical Constraining-Core Configuration oo... cece cee ceeeeenee 43 Figure 5-3A = Multilayer Metal Core Printed Board with Two Symmetrical Copper-Invar-Copper Constraining Cores (when the Copper- Invar-Copper planes are connected to the plated-through hole, use thermal relief per Figure 9-4) wow 43 Figure 5-3B Symmetrical Constraining Core Printed Board with a Copper-Invar-Copper Center Core Figure 5-4 Advantages of Positional Tolerance Over Bilateral Tolerance, mm [in] «0.00... 46 Figure 5-5 Datum Reference Frame ou... eee 47 Figure 5-6 Example of Location of a Pattern of PTHs, mm [In] oo. 48 Figure 5-7 Example of a Pattern of Tooling/Mounting Holes, mm [in] Figure 5-8 Example of Location of a Conductor Pattern Using Fiducials, mm [in]... 49 Figure 5-9 Example of Printed Board Profile Location and Tolerance, mm [in] .......c eee 50 Figure 5-10 Example of a Printed Board Drawing
Utilizing Geometric Dimensioning and Tolerancing, mm [in] ...
Figure 5-11 Figure 5-12
Figure 5-13
Figure 6-1 Figure 6-2 Figure 6-3 Figure 6-4
Figure 6-5
Figure 6-6
Figure 6-7 Figure 7-1
Figure 7-2
Figure 8-1
Figure 8-2 Figure 8-3
Figure 8-4 Figure 8-5 Figure 8-6
Figure 8-7
Figure 8-8
Figure 8-9
Figure 8-10 Figure 8-11 Figure 8-12 Figure 8-13 Figure 8-14 Figure 8-15 Figure 8-16 Figure 8-17
Figure 8-18 Figure 8-19
Figure 8-20 Figure 8-21 Figure 8-22 Figure 8-23 Figure 8-24
Figure 8-25 Figure 8-26
Fiducial Clearance Requirements ............0. 51 Printed Board Panelization/
Palletization, MM ..........cccccccccccecceessceeseeeeeeeee 51 Example of Connector Key Slot
Location and Tolerance, mm [in] ..........0.0 52 Voltage/Ground Distribution Concepts .......... 54 Single Reference Edge Routing ........... 55
Circuit Distribution ...
Transmission Line Printed Board COMSTIUCTION oo... .seseeseceseseseseseseseeeeeteeeeeteseeeees 59
Capacitance vs. Conductor Width and Dielectric Thickness for Microstrip Lines,
MM [IN] eee cece eee eee cee neeeee 63 Capacitance vs. Conductor Width and
Spacing for Striplines, mm [in] «0.0.0... 64 Single Conductor Crossover ou... 64 Component Clearance Requirements for Automatic Component Insertion... 68 Relative Coefficient of Thermal Expansion (CTE) Comparison oo... 71 Component Orientation for Boundaries
and/or Wave Solder Applications 0.00.00... 75 Component Body Centering «0.0.00. 75 Axial-Leaded Component Mounted Over CONGUCHOIS oe eeeeceecceeeeesesesestseeeeeteeneeseseseees 76 Uncoated Board Clearance ou... 76
Clamp-Mounted Axial-Leaded Component ... 76 Adhesive-Bonded Axial-Leaded
Component 0.0... cece eee eeeeeeenee 76 Example of Filleting Compared to Bonding .. 77 Mounting with Feet or Standoffs wo... 77 Heat Dissipation Examples ........cc ee 78 Lead Bends
Typical Lead Configurations . 79 Typical Keying Arrangement 82
Printed Board Edge Tolerancing .
Lead-In Chamfer Configuration .........0c 83 Two-Part Connector ........ccccceceseeseeeseeeeeeeeeeee 83 Edge-Board Adapter Connector uu... 83 Round or Flattened (Coined) Lead Joint
Description o.... eee ee eeceeeeeeeee 85 Standoff Terminal Mounting, mm [in] ............ 85
Dual Hole Configuration for Interfacial and Interlayer Terminal Mountings .
Partially Clinched Through-Hole Leads Dual In-Line Package (DIP) Lead Bends ...... 88
Solder in the Lead Bend Radius ............... 88 Two-Lead Radial-Leaded Components ......... 89 Radial Two-Lead Component
Mounting, mm [in] ....... eee 89 Meniscus Clearance, mm [in] ........0c ee 89
“TO” Can Radial-Leaded Component, mm [in] ..
viii
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November 2012
IPC-2221B
Figure 8-27 Figure 8-28 Figure 8-29
Figure 8-30
Figure 8-31
Figure 8-32
Figure 8-33 Figure 8-34 Figure 8-35
Figure 8-36 Figure 8-37 Figure 8-38 Figure 8-39
Figure 8-40
Figure 8-41
Figure 8-42 Figure 8-43 Figure 8-44
Figure 9-1 Figure 9-2 Figure 9-3 Figure 9-4 Figure 10-1 Figure 10-2
Figure 10-3 Figure 11-1
Figure 11-2 Figure 11-3 Figure 11-4 Figure 12-1
Figure 12-2
Figure 12-3
Figure 12-4
Figure A.2-1 Figure A.2-2 Figure A.3-1 Figure A.3-2 Figure A.4-1
Perpendicular Part Mounting, mm [in] .......... 90 Flat-Packs and Quad Flat-Packs ...........0006 90
Examples of Configuration of Ribbon Leads for Through-Hole Mounted Flat-PackS .......ccccccseseceeeeesessscseeeeeeeeeeesesseeeenens 90
Metal Power Packages with Compliant Leads .
Metal Power Package with Resi
SPacers woes eec ee ceeeeeee 90 Metal Power Package with Noncompliant
1 -5- Co: n 90 Examples of Flat-Pack Surface Mounting ..... 91 Round or Coined Lead ..........:ccceceeceseseeeeeeee 92 Configuration of Ribbon Leads for Planar
Mounted Flat-Packs ..........:ccccsceceeeeseseseeeeeee 92
Heel Mounting Requirements ... TSSOP Package Construction . SQFP Package Construction ...
Examples of Ball Grid Array (BGA) Package Construction .
Ceramic Column Grid Array (CGA)
Package Construction wo... cece 94 Land Grid Array (LGA) Package COMSTIUCTION oo... eeeeceseceeesseseeeseseesseeeeeeeeseseteeee 94
Quad Flat No-Lead (QFN) Construction ....... 95 Small Outline No-lead (SON) Construction .. 95
Pullback Quad Flat No Lead (PQFN) Construction
Examples of Modified Land Shapes . External Annular Ring
Internal Annular Ring ou... eee 97 Typical Thermal Relief in Planes uw... 97 Etched Conductor Characteristics ............... 104 Example of Conductor Beef-Up or
NeCk-DOWN .......scseseseseseeesessseseeteeeeeetesseseesens 105
Conductor Optimization Between Lands ..... 105 Flow Chart of Printed Board Design/
Fabrication Sequence ow... eee 107 Multilayer Printed Board Viewing .............. 108 Gang Solder Mask Window .........c ee 109 Pocket Solder Mask Window ..........:::00+ 109 Panel Utilization among IPC-2221B
Conformance Coupon Designs ..........0..0. 112
Panel Utilization among Legacy Conformance Coupon Designs ..........0..0. 113
Example Stack-up for a Ten Layer Printed Board .........ccccccecsssssseseeeesesesseeeeeeaes 113
Systematic Path for Implementation of
Statistical Process Control (SPC) 0.0... 116 AB/R Coupon Layout, mm [in] ..........cee 119 AB/R Coupon Example Layers .........:.:0 120
A/R Coupon Layout, mm [in]
A/R Coupon Example Layers
B/R Coupon Layout, mm [in] .
Figure A.5-1 Figure A.5-2 Figure A.6-1 Figure A.6-2 Figure A.7-1 Figure A.7-2 Figure A.8-1
Figure A.8-2
Figure A.8-3
Figure A.9-1
Figure A.9-2
Figure A.10-1 Figure A.10-2 Figure A.11-1 Figure A.11-2 Figure A.12-1
Figure A.12-2 Figure A.12-3
Figure B.2-1 Figure B.2-2
Figure B.2-3 Figure B.2-4
Figure B.3-1 Figure B.3-2
Figure B.4-1 Figure B.5-1
Figure B.6-1 Figure B.6-2 Figure B.6-3
Figure B.6-4
Figure B.7-1
Figure B.8-1 Figure B.8-2 Figure B.9-1 Figure B.10-1 Figure B.10-2 Figure B.10-3 Figure B.11-1
E Coupon Layout, mm [in] E Coupon woe cece eee S Coupon Layout, mm [in] S Coupon Example Layers ... W Coupon Layout, mm [in]
W Coupon Layout
D Coupon Layout with A and B Features, mm [in] ..
D Coupon Example Layers with A and
B Features .......ccccccsescecesesesessesseeeeeeeeeeeseeeeene 133 D Coupon Layout with Non-through Via
B Features, mm [In] 0... eee 133 G Coupon Layout, mm [in] .... « 135 G Coupon Example Layers 136 H Coupon Layout, mm [in] .... . 137 H Coupon Example Layers ........ ee 138 P Coupon Layout, mm [in]... 139 P Coupon Example Layers oo... 139 Z Coupon Layout (Microstrip and
edge-coupled microstrip), mm [in] ............... 140 Z Coupon Example Layers ou... 141 Z Coupon Layout (Microstrip and
edge-coupled microstrip using
alternative test points), mm [in] ............ 141 Test Coupons A and B, mm [in] ........ 143
Test Coupons A and B (Conductor
Detail), mm [in] 144
145
Test Coupon A/B, mm [in] Test Coupon A/B (Conductor Detail),
MM [IN] oe cece cece eee eeeeeee 146 Coupon E, mM wee eens 147 “Y” Pattern for Chip Component
Cleanliness Test Pattern .........ccceeceeee 147 Test Coupon S, mm [IN] 0. ee 148 Test Coupon M, Surface Mounting
Solderability Testing, mm [in] «0.0.0... 149 Test Coupon D, mm [in] uu... 150 10 Layer Example oo... eee 151
Example of a 10 Layer Coupon D, Modified to Include Blind and Buried
VIAS ooeeeeececeeeeceeecseseeseeeeseesseeeeesesestssseeeessesetes 152 Test Coupon D for Process Control of 4 Layer Printed Boards oo. c eee 153
Test Coupon G, Solder Resist Adhesive,
mm [in] 153 Optional Coupon H, mm [in] ........ ee 154 Comb Pattern Examples ........cc eee 155 Coupon C, External Layers Only, mm [in] .. 155 Test Coupon F, mm [in] 157 Test Coupon R, mm [in] .. . 158
Worst-Case Hole/Land Relationship ........... 158
Test Coupon N, Surface Mounting Bond
Strength and Peel Strength, mm [in] . . 159
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IPC-2221B
November 2012
Figure B.12-1 Test Coupon X, mm [in] ou... ee 161 Figure B.12-2 Bending Test oo... ccc 161 Tables
Table 3-1 PCB Design/Performance Tradeoff Checklist .......cccseseseseseesesesesessssseeeeeeeeeeeseseeeeeees 6 Table 3-2 Component Grid Areas... eee 19 Table 4-1 Typical Properties of Common Dielectric Materials .........ccscsccecececeeesssescseeeeeseetesseeeeeeseee 23 Table 4-2 Final Finish and Coating Requirements ........ 26 Table 4-3 Surface and Hole Copper Plating Minimum Requirements for Buried Vias >2 Layers, Through-Holes, and Blind Vias uo... 27 Table 4-4 Surface and Hole Copper Plating Minimum Requirements for Microvias (Blind and Buried) 0... eee 27 Table 4-5 Surface and Hole Copper Plating Minimum Requirements for Buried Via Cores (2 Layers) Table 4-6 Surface Finishes Table 4-7 Gold Plating Uses Table 4-8 ENIG Surface Finish Advantages and Disadvantages 0... cece 30 Table 4-9 ENIG/EG Surface Finish Advantages and Limitations Table 4-10 ENEPIG Surface Finish Advantages and Disadvantages Table 4-11 Immersion Silver Surface Finish Advantages and Disadvantages .......cc eee 31 Table 4-12 Immersion Tin Surface Finish Advantages and Disadvantages .. Table 4-13 OSP Surface Finish Advantages and LiMitatiONS oo... eecceceeeceees ee eeeteeeeeeeeteeeeeeeeeseae 33 Table 4-14 Copper Foil/Film Requirements ........0..000. 35 Table 4-15 Metal Core Substrates .........ccccccseeeeeeeseseee 36 Table 4-16 Typical Minimum Solder Mask Clearances AN DAM ou... cecccesesceeeseseeessseseeeeeeeeeeeseseeeeee 37 Table 4-17 Conformal Coating Types and Thickness Range Table 4-18 Conformal Coating Functionality «0.0.0... 38 Table 5-1 Fabrication Assumptions and Considerations .........:.cceeesseeeeeeeeeeeeeeeeseeneee 40 Table 5-2 PC Card Form Factor Substrate Dimensions .
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le 5-3 le 6-1 le 6-2
le 6-3
le 7-1 le 7-2 le 7-3
le 7-4
le 9-1
le 9-2 le 9-3 le 9-4 le 9-5 le 9-6
le 10-1
le 10-2
le 12-1 le 12-2
le A.1-1 le A.2-1 le A.3-1 le A.4-1 le A.5-1 le A.6-1 le A.7-1 le A.8-1 le A.9-1 le A.10-1 le A.11-1 le A.12-1
le B.1-1
Typical Assembly Equipment Limits .............. 45 Electrical Conductor Spacing ou... 57
Typical Relative Bulk Dielectric Constant of Printed Board Material «0.0.0.0... 60
Example Plane Sequences for a Six Layer Printed Board
Effects of Material Type on Construction
Emissivity Ratings for Certain Materials . Printed Board Heatsink Assembly
Preferences
Comparative Reliability Matrix Component Lead/Termination Attachment .............:0:c00+ 70 Minimum Standard Fabrication Allowance
for Interconnection Lands ..........:ccceceeeee 96 Annular Rings (Minimum) ........0.ccc eee 97
Minimum Drilled Hole Size for Buried Vias ... 99 Minimum Drilled Hole Size for Blind Vias ..... 99
Minimum Hole Location Tolerance, dtp ....... 101 Through-Hole Diameters Minimum and Maximum and Aspect Ratio, mm [in] .......... 102 Internal Layer Foil Thickness After
ProceSSiNg .....cccc cece eee eee eeeeeieeee 103 External Conductor Thickness After
Plating oo. cece ences 103 Appendix A Coupon Requirements .............. 111 Appendix B (Legacy) Coupon
Requirements 0... cece 111 IPC Coupons oo... eeeeeeeee 117 AB/R Coupon Parameters, mm [in] ............. 118
A/R Coupon Parameters, mm [i B/R Coupon Parameters, mm [i E Coupon Parameters, mm [in S Coupon Parameters, mm [in W Coupon Parameters, mm [in D Coupon Parameters, mm [in G Coupon Parameters, mm [in H Coupon Parameters, mm [in P Coupon Parameters, mm [in
Z Coupon Parameters, mm [in
IPC-2221 Legacy Coupons ..
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November 2012 IPC-2221B
Generic Standard on Printed Board Design
1 SCOPE
This standard establishes the generic requirements for the design of organic printed boards and other forms of component mounting or interconnecting structures, including PC card form factors. The organic materials may be homogeneous, rein- forced, or used in combination with inorganic materials; the interconnections may be single, double, or multilayered.
1.1 Purpose The requirements contained herein are intended to establish design principles and recommendations that shall be used in conjunction with the detailed requirements of a specific interconnecting structure sectional standard (see 1.2) to produce detailed designs intended to mount and connect components. This standard is not intended for use as a performance specification for finished printed boards nor as an acceptance document for electronic assemblies.
1.2 Documentation Hierarchy This standard identifies generic physical design principles, and is supplemented by various sectional standards that provide sharper focus on specific aspects of printed board technology. These include:
IPC-2222 Rigid organic printed board design
IPC-2223 Flexible printed board design
IPC-2225 Organic, MCM-L, printed board design
IPC-2226 High Density Interconnect (HDI) printed board design
The documents are a part of the Family of Design Documents which is identified as IPC-2220. The number IPC-2220 is for ordering purposes only and includes this standard and the four listed above.
Note: IPC-2224, a sectional design standard for PC card form factors, was cancelled by the IPC. Relevant PC form factor design information has been transferred to this revision of IPC-2221 and to IPC-2222.
1.3 Presentation All dimensions and tolerances in this standard are expressed in hard SI (metric) units and parenthetical soft imperial (inch) units. Users of this standard are expected to use metric dimensions. All dimensions greater than or equal to 0.1 mm [0.0039 in] will be expressed in millimeters and inches. All dimensions less than 0.1 mm [0.0039 in] will be expressed in micrometers and microinches.
1.3.1 Dimensional Units The following is taken from National Institute of Standards and Technology - Metric Informa- tion and Conversions: “Beginning January 1, 2010, the European Union Council Directive 80/181/EEC (Metric Directive) allowed the use of only metric units, and prohibited the use of any other measurements for most products sold in the Euro- pean Union (EU). The Metric Directive made the sole use of metric units obligatory in all aspects of life in the European Union, extending to areas such as product literature and advertising.”
Most component datasheets are provided in metric units. Many printed board designers spend a lot of time converting between imperial (inch) and SI (metric). Round-off errors, when converting units, can result in inaccuracies that result in marginal or failed designs. However, the printed board fabrication vendors often default to imperial units. Electronic Com- puter Aided Design (ECAD) tools accommodate both metric and imperial library components being placed on the same printed board because dimensional precision is large enough to describe most standard components accurately.
Problems arise when importing information from third party software or trying to mix units during printed board layout. For example, if a portion of the printed board design is an imported Drawing Exchange Format (.DXF) file with metric units that needs to interface with a digital portion done in imperial units, a problem can occur where the data from the two grids are mixed. Unlike importing from libraries, a conversion to printed board units is not always done when importing DXF.
While a user can convert printed board units from metric to imperial in modern day tools without problems, this should not be done too often during the design phase as repeated conversions can introduce unexpected errors. A single set of units should be used in the layout of the printed board. If imported data is in metric units, the layout portion of the process should use metric units. Once the layout is complete and verified, the designer can convert the printed board to imperial units for documentation, if necessary.
1.4 Interpretation “Shall,” the imperative form of the verb, is used throughout this standard whenever a requirement is intended to express a provision that is mandatory. Deviation from a “shall** requirement may be considered if sufficient data is supplied to justify the exception.