docs/XLamp-PCB-Thermal.pdf — Oasis datasheet

PRODUCT DESIGN GUIDE

Optimizing PCB Thermal Performance for XLamp® LEDs

TABLE OF CONTENTS

INtFOGUCTION 00. eee cece ee eeeeeeeeeeeeeeeeeseeteseeneseeneeteicetesestsatseeeteneeneees 1

Thermal Management Principles.............c.ccceceseseeseseeeseseseeeeeeseeeeeeees 2 XLamp® LED Thermal Characteristics ........0...c.cccseseeseseeeeeeteees 2

PCB Thermal Characteristics

Designing Thermal Vias Open Vias vs. Filled Via Thermal Performance Simulations

Surface Thermal Dissipation ..........0..ceccceeceseseseeteteseeeseeeeeetenenes 7 Thermal Dissipation with Vias..........ceceeceeeseeeeteteeseeeeeeteeees 8 Combined Surface and Via Studies ..0.0..0.0..0 cece 10 Summary Results of Thermal Simulations... 12 Temperature Verification Measurements...........ccceceeeeeeeeeteeeeeee 13 Recommended Board Layouts..............ccccceeeceeseeseseeeseeeseees 15

FR-4 Boards for XLamp XP and XT LED Packages FR-4 Boards for XLamp XB LED Package. FR-4 Boards for XLamp MX LED Package we FR-4 Boards for XLamp ML LED Package .............:cceeeeeees 20

Chemical Compatibility... cece eeeeeeeeseeeeeeeeeneseeneeeeee 21 Referens... ceesseeeeesteeseeseeeeseeeseesesseassesaeseeeeseeeeeeesees 21

INTRODUCTION

This application note outlines a technique to assist with the development of cost-effective thermal management for the XT, XP, XB, MX and ML families of XLamp® LEDs.

One of the most critical design parameters for an LED illumination system is the system's ability to draw heat away from the LED junction. High operating temperatures at the LED junction adversely affect the performance of LEDs, resulting in decreased light output and lifetime.’ To properly manage this heat, specific practices should be followed in the design, assembly and operation of LEDs in lighting applications.

This application note outlines a technique for designing a low-cost printed circuit board (PCB) layout that optimizes the transfer of heat from the LED. The technique involves the use of FR-4-based PCBs, which cost less than metal core printed circuit boards (MCPCB), but have greater thermal resistance. The use of metal- lined holes or vias underneath LED thermal pads is a method to dissipate heat through an FR-4 PCB and into an appropriate heat sink.

XLamp LEDs are designed with an electrically isolated thermal path. Cree LED pioneered this LED feature almost ten years ago to enable the use of metalized vias in FR-4 PCBs. For certain illumination systems design, thermal vias enable the use of FR-4 circuit boards instead of metal core circuit boards. This can deliver system cost savings in circuit board and heat sink selection.

This application note serves as a practical guideline based on heat transfer fundamentals and includes suggestive, but not definitive, simulation and measurement data. Cree LED advocates this technique as appropriate design for certain lighting applications and encourages Cree LED’s customers to evaluate this option when considering the many thermal management techniques available. For additional guidelines on LED thermal management,

refer to the Thermal Management application note.

1 See the Long-Term Lumen Maintenance application note.

Cree LED / 4001 E. Hwy. 54, Suite 2000 / Durham, NC 27709 USA / +1.919.313.5330 / www.cree-led.com

© 2010-2023 Cree LED. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and the Cree LED logo are registered trademarks of Cree LED. This document is provided for informational purposes only and is not a warranty or a specification. For product

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

THERMAL MANAGEMENT PRINCIPLES

The technique in this application note is not recommended for XLamp LEDs that consume more than 5 W of power, such as MT-G2. This technique can be used for low-power applications. XLamp® LED Thermal Characteristics

All XLamp LED packages have an electrically isolated thermal pad. The pad provides an effective channel for heat transfer and optimizes thermal resistance from the LED chip junction to the thermal pad. The pad is electrically isolated from the anode and cathode of the LED and can be soldered or attached directly to grounded elements on the board or heat sink system.

Anode

LED chip

Thermal pad

Cathode

Figure 1: XLamp XP LED package

Heat is conducted from the LED package through the thermal pad and into a PCB that should be mounted to a heat sink to transfer the conducted heat into the operating environment.? Tables 1 and 2 list typical thermal resistance values (junction to solder point) for various XLamp series LEDs.

Table 1: Typical thermal resistance values for XLamp white LEDs

Thermal Resistance (°C/W)

Color [tie | Se [tee [eee [ee eo | ae | White (cool, neutral, warm) | 25 | 13 | 9 | " | 5 | 65 | 12 | 58 | 2 | 28 |

Table 2: Typical thermal resistance values for XLamp color LEDs n/a indicates an LED that Cree LED does not offer

Thermal Resistance Color (c/w)

Royal blue

Blue | 8s | nm | 57 Green | 1 | 2 | 9 Amber | 23 | 125 | 75 Red | 19 | 15 | 65 Red-orange | n/a | 11.5 | 6.5

2 For subsequent discussion and simulation in this document, we assume the PCB is mounted to an infinite heat sink that maintains the back side of the board at 25 °C.

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

PCB Thermal Characteristics FR-4

FR-4 is one of the most commonly used PCB materials and is the National Electrical Manufacturers Association (NEMA) designation for a flame retardant, fiberglass-reinforced epoxy laminate. A by-product of this construction is that FR-4 has very low thermal conductivity. Figure 2 below shows a typical cross-sectional geometry for a two-layer FR-4 board.

Thermal pad

Top layer Cu Solder mask

FR4 dielectric

Bottom layer Cu ENIG

Figure 2: FR-4 cross-sectional geometry (not to scale)

Using the thermal conductivity values in Table 3 below, the total thermal resistance for an FR-4 board can be calculated by adding the thermal resistances of the layers.

Boce = Braver + Stayero + 9) +6 (1)

layer1 " Tlayer2 * “layers *** * “layerN,

For a given layer the thermal resistance is given by the formula: 6=1/(kxA) (2) where | is the layer thickness, k is the thermal conductivity, and A is the area normal to the heat source.

For a 1.6-mm thick star board approximately 270 mm”, the calculated through-plane thermal resistance is approximately 30 °C/W. Bear in mind that this calculation is one-dimensional and does not account for the size of the heat source, spreading, convection thermal resistances or boundary conditions. If a smaller heat source size is considered, for example 3.3 mm x 3.3 mm, the resulting one- dimensional thermal resistance increases to over 700 °C/W.

Table 3: Typical thermal conductivities of FR-4 board layers

Layer/Material Thickness (um) Thermal conductivity (W/mK)

SnAgCu solder 75 58 Top layer copper 70 398 FR-4 dielectric 1588 0.2 Bottom layer copper 70 398 Electroless Nickel/Immersion Gold (ENIG) 5 4.2

Metal-Core Printed Circuit Board

A simple one-layer MCPCB is comprised of a solder mask, copper circuit layer, thermally conductive dielectric layer, and metal core base layer, as shown below in Figure 3. These three layers are laminated and bonded together, providing a path for the heat to dissipate. Often the metal substrate is aluminum, though steel and copper can also be used.

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

Heat source

Thermal pad

Top layer Cu ‘Solder mask

Dielectric layer

Al substrate

Figure 3: MCPCB cross-sectional geometry (not to scale)

Using the thermal conductivity values in Table 4 below, the one-dimensional through-plane thermal resistance for a 1.6-mm-thick star board of approximately 270 mm? is roughly 0.2 °C/W. If a smaller heat source size is considered, the resulting thermal resistance is 5.3 °C/W. In this case, the limiting factor is the PCB dielectric.

Table 4: Typical thermal conductivities of MCPCB layers

Layer/Material Thickness (um) Thermal conducti (W/mK)

SnAgCu solder 75 | 58 Top layer copper | 70 | 398 PCB dielectric | 100 | 22 Alplate | 1588 | 150

Designing Thermal Vias

An inexpensive way to improve thermal transfer for FR-4 PCBs is to add thermal vias - plated through-holes (PTH) between conductive

layers. Vias are created by drilling holes and copper plating them, in the same way that a PTH or via is used for electrical interconnections between layers.

Thermal vias

Top layer Cu

FR4 dielectric ‘Solder mask

Bottom layer Cu Figure 4: FR-4 cross-sectional geometry with thermal vias (not to scale)

© 2010-2023 Cree LED. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and the Cree LED logo are CLD-AP37 registered trademarks of Cree LED. This document is provided for informational purposes only and is not a warranty or a specification. For product REV 4

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

Solder mask 0.6 mm dia. via with

35 um plating

0.3 mm dia. via with 35 um plating

Top layer Cu

FR4 dielectric

Bottom layer Cu

Figure 5: Cross-sectional geometry of small and large thermal vias in FR-4 substrate

Adding vias in an appropriate way will improve the thermal resistance of an FR-4 board. The thermal resistance of a single via can be calculated by the same formula, 8 = | / (k x A). Using the values in Table 5, a single solder-filled via with a diameter of 0.6 mm results in

(1.588 x 10%) / (58 x (J x (0.5 x 0.6 x 10*)*)) = 96.8 °C/W. However, when N vias are used, the area increases by a factor of N ,.., resulting in:

vias?

Bias =! / (Nyigg X KX A) (3)

vias

Note that this is applicable only if the heat source is directly normal to the thermal via; otherwise, the resistance increases due to thermal spreading effects. To calculate the total thermal resistance for the region underneath (or normal to) the LED thermal pad, the equivalent thermal resistance for the dielectric layer and vias must be determined. For simplicity, the two resistances are treated as parallel applying this formula.

Gas werd = [(1/6,,,.) + (1/84) 1" 6

Using the values in Table 5, for a 270 mm? board with five 0.6-mm-diameter solder-filled vias results in an approximate thermal resistance of 12 °C/W, a 60% improvement over the initial 30 °C/W derived from the data in Table 3.

Table 5: Typical thermal conductivities of FR-4 board layers including thermal vias

Layer/Material Thickness (um) Thermal condu ity (W/mK)

SnAgCu solder 75 58 Top-layer copper 70 398 FR-4 1588 0.2 Filled vias (SnAgCu) 1588 58 Bottom-layer copper 70 398 Solder mask (optional) 25 0.2

Open Vias vs. Filled Vias

Open vias result in a higher thermal resistance than filled vias because the area normal to the heat source is reduced per the formula: A=)x(Dxt-t’) (5)

where D is the via diameter and t is the plating thickness.

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

For a 0.6-mm diameter via with 35 ym (1 0z.) copper plating, the area normal to the thermal pad is only 0.06 mm?compared to 0.28 mm? for a solder-filled via, resulting in a thermal resistance of 64 °C/W per via compared to 42 °C/W if filled with solder or 14 °C/W if filled completely with copper.

In general, increasing plating thickness during PCB production improves the thermal resistance of vias. In the example above, increasing the plating thickness to 70 ym (2 oz.) lowers the thermal resistance to 34 °C/W per via. Consult your PCB manufacturer to determine if thicker plating is feasible.

Non-filled vias may become filled with solder during reflow. However, depending on a number of factors, this may not occur reliably and as a result, the vias will conduct heat less effectively.

An option to creating a solid via during the plating process in PCB production is to fill the vias with a thermally conductive material such as epoxy as part of the PCB fabrication process. This adds an additional step to fabrication and may increase the cost of the board.

Solder voiding in open PTH vias

Figure 6 shows an example of unfilled vias after reflow. Figure 7 shows an example of solder voids underneath the device (shown in red). The voids increase the thermal resistance of the thermal interface. Also, the solder may overfill the hole leading to bumps on the bottom of the board that can reduce the contact area between the board and the heat sink.

Steps can be taken to limit the amount of solder wicking. One way is to maintain a via diameter smaller than 0.3 mm. With smaller vias, the surface tension of the liquid solder inside the via is better able to counter the force of gravity on the solder. If the via structure is constructed following the guideline above, holding the inside via diameter to around 0.25 mm — 0.3 mm, minimal solder wicking is achieved. The drawback to this approach is that smaller open vias result in a higher overall thermal resistance.

Figure 6: Unfilled vias Figure 7: Solder voiding (not to scale)

Another technique for limiting solder wicking involves using solder mask to restrict the flow of solder from the top side of the PCB to the bottom side. One process, called tenting, uses solder mask to prevent solder from either entering or exiting the thermal vias, depending on the side of the board on which the solder mask is placed. Tenting the bottom side with solder mask to cover and plug the thermal vias can prevent solder from flowing down into the vias and onto the bottom of the board. In top-side via tenting, small areas of solder mask are placed over the thermal vias on the top side of the PCB to prevent solder from flowing into the vias from the top side of the board.

Figure 8: Tented vias with bottom-side solder mask (not to scale)

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

THERMAL PERFORMANCE SIMULATIONS

This section presents results obtained from computational thermal analysis for a series of PCB configurations.*

Surface Thermal Dissipation

The first configuration, shown in Figure 9, consists of a star FR-4 PCB with varying widths of the thermal pad and two board thicknesses (0.8 mm and 1.6 mm); the bottom copper layer is solid and there are no thermal vias.

Minimum trace: 3.3mm wide Trace: 6.0mm wide Trace: 10.0mm wide Maximum trace: 20.0mm wide

Figure 9: Variation in thermal pad width on top side of PCB

The analysis results in Chart 1 show that, for the 1.6-mm thick board, increasing the thermal pad width beyond 12 mm provides little improvement and, for the 0.8-mm thick board, improvement diminishes beyond a 16-mm width.

70 FR4 No Vias: Top Trace Size- Solder point through board

—— 1.6mm thick FR4 No Vias

—— 0.8mm thick FR4 No Vias 50

Thermal Resistance, Solder point through Board (°C/W)

0 5 10 15 20 25 Length/Width of top trace (mm) Chart 1: Thermal resistance for FR-4 PCB with no vias with varying thermal pad size

The next configuration is the same as the first except the board is an MCPCB. Chart 2 shows there is little benefit to extending the thermal pad width beyond 6 mm for either board thickness.

3 Cree LED used Ansys Design Space, www.ansys.com/products/structural-mechanics/products.asp

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

5.0 -___ MCPCB: Top Trace Size- Solder point through board

—— 1.6mm thick MCPCB 45

—— 0.8mm thick MCPCB

4.0

3.5

3.0

2.0

1.0

Thermal Resistance, solder point through Board (°C/W)

0.5

0.0

0 5 10 15 20 25 Length/Width of top trace (mm)

Chart 2: Thermal resistance for MCPCB with varying thermal pad size

Thermal Dissipation with Vias

Chart 3 shows the effects of various filling materials for 0.7-mm diameter vias with 1-mm center-to-center spacing for both 1.6-mm and 0.8-mm board thicknesses, shown in Figure 10. The analysis data indicate solid copper filled vias result in lower thermal resistance and unfilled vias deliver higher thermal resistance. A via filled with conductive epoxy performs only slightly better than an unfilled via.

Figure 10: FR-4 board with five and fifteen 0.7-mm-diameter vias and 1-mm pitch

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

Unfilled

1.6mm thick FR4 PCB, 5 vias 0.8mm thick FR4 PCB, 5 vias A1.6mm thick FR4 PCB, 15 vias 0.8mm thick FR4 PCB, 15 vias

Solder

i Copper

onductive Epo!

25 ie) 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 Via Thermal Conductivity (W/mK)

Chart 3: Thermal resistance for FR-4 vias filled with materials of differing conductivity

Chart 4 shows the effect of changing the diameter and number of vias. This chart assumes the vias are filled with SnAgCu solder. As expected, the larger the diameter of the via, the lower the thermal resistance becomes. Increasing the number of vias shows considerable improvement for smaller via diameters.

30 Via Size

——91 Vias, 1.6mm Pca

Thermal Resistance, solder point through board (°C/W)

oO o1 0.2 03 04 os 0.6 07 08 09 Via Diameter (mm)

Chart 4: FR-4 PCB with various via diameters and numbers of vias

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

The next case considers the effect of varying the number of thermal vias as shown in Figure 11. These vias are solid-plated copper with a diameter of 0.254 mm (0.010 in.) and center-to-center spacing of 0.635 mm (0.025 in.). The results in Chart 5 indicate that increasing the number of vias beyond fourteen shows little improvement. (This is the maximum achievable density of the area normal to the LED thermal pad.)

Figure 11: FR-4 board with varying numbers of thermal vias (2, 6, 8, 14, 58, and 102)

20 -____________ Filled Via Count: 610mil, 25.4mil pitch

18 1.6mm thick FR4 PCB 0.8mm thick FR4 PCB

16 —--- 1.6mm MCPCB

=--= 0.8mm MCPCB

Thermal Resistance, Solder point through Board (°C/W)

oO 20 40 60 80 100 120 # of Filled Copper Vias

Chart 5: Thermal resistance values FR-4 board for varying numbers of copper-filled thermal vias

Combined Surface and Via Studies

The next configuration is an FR-4 PCB with fourteen 0.254-mm diameter copper plated vias with the thermal pad widths shown in Figure 12. The bottom copper layer is solid. The data in Chart 6 show that, beyond a 6-mm width, there is little improvement in thermal resistance.

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

Sa) Sa) Sa)

Figure 12: FR-4 PCB with 14 thermal vias and varying top thermal pad widths (3.3, 4.0, 6.0, 10.0, 14.0, 20.0 mm)

9 >————— FR4 14 vias: Top Trace Size- Solder point through board 8 —— 1.6mm thick FR4 PCB = —— 0.8mm thick FR4 PCB $ 2 7 8 & S 6 8 = = 5 2 3 4 & g 5 3 2 é 3 2 E 2 = 1 0 T T T T 1 i) 5 10 15 20 25 Trace Width (mm)

Chart 6: Thermal resistance of FR-4 PCB with 14 vias and varying thermal pad widths

Finally, the previous scenario is repeated with the bottom thermal pad widths shown in Figure 13. The results, shown in Chart 7, indicate that there is a small difference in thermal resistance that decreases as the width of the bottom pad increases.

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

aris LS

Figure 13: FR-4 PCB with 14 thermal vias and varying bottom thermal pad widths (3.3, 4.0, 6.0, 10.0, 14.0, 20.0 mm)

10 »— FR4 14 vias: Top + Bottom Trace Size- Solder point through board Full Backside & Changing Frontside_ 1.6mm PCB

9 Full Backside & Changing Frontside_ 0.8mm PCB = Changing Back & Frontside, 1.6mm PCB 3 8 ——Changing Back & Frontside, 10.8mm PCB z 5 8 a 7 s & 3 4 s 6 z 3 a 5 3 3 °° ” 4 g 2 5 g 3 3 @ 3 E 2 3 2 E

1°) T T T T 1

oO 5 20 25

10 15 Top + Bottom Trace Width (mm)

Chart 7: Thermal resistance of FR-4 PCB with 14 vias and varying top and bottom thermal pad widths Summary Results of Thermal Simulations

1. The results from the various simulations show that the dielectric thickness should be 0.8 mm to achieve the lowest possible thermal resistance for an FR-4 board.

© 2010-2023 Cree LED. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and the Cree LED logo are CLD-AP37 1 2 registered trademarks of Cree LED. This document is provided for informational purposes only and is not a warranty or a specification. For product REV 4

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

2. Although making the vias as large as possible reduces thermal resistance, the cost of manufacturing the board must also be considered. Larger unfilled vias introduce the possibility of the vias becoming partially filled during the soldering process. Smaller, closely spaced vias are a better solution.

3. Finally, adding additional vias and increasing the width of the thermal pad beyond a certain point have diminishing returns because of thermal spreading resistance.

Based on these conclusions, on page 15 Cree LED recommends an optimal thermal pad size, via size and spacing that is both thermally effective and manufacturable.

TEMPERATURE VERIFICATION MEASUREMENTS

Because LED junction temperature affects LED lifetime, Cree LED recommends performing a thermal verification test on the LED-board assembly under real-life conditions.*

This section illustrates practical LED board thermal measurement using thermocouples, which offers some corroboration for the simulations on which we base our recommendations.

Figure 14 shows a type-K thermocouple attached to the top copper layer close to the thermal pad. The solder mask (if present) should be removed to solder the thermocouple to the board. Alternately the thermocouple can be attached using a thermal epoxy or aluminum tape. If more than one LED is on the board, the lamp with the highest expected temperature should be selected. Another thermocouple is attached to the back of the heat sink using thermal epoxy. A third thermocouple is used to measure the ambient (air) temperature.® The thermocouple wires are held in place with Kapton® tape. To calculate the actual heat sink to ambient thermal resistance, divide the difference between Ths and Ta by the power of the heat source.

Thst ssnanionn

Ths2

Figure 14: Thermocouple placement

Table 6 below contains data from five sets of five XLamp XP-E LEDs mounted on star boards. The first four sets are 1.6-mm thick FR-4 boards with via layouts similar to Figure 12 and Figure 13 with 10-mm wide bottom thermal pads; the last set is 1.6-mm thick aluminum clad boards. The PCBs were mounted to a heat sink with thermal adhesive.* Measurements of the forward voltage (V,) and

4 Normally the junction temperature cannot be measured directly and must be derived from the temperature measured at a reference point on the top copper layer. 5 At least 2 mm away from the heat sink and/or illumination source and not in the path of illuminance. 6 Aavid Thermalloy part number 374424B000356G, with Chomerics THERMATTACH® 1411 thermal tape for FR-4; CTS Electronics part number BDN10-5CB/A01for MCPCB

© 2010-2023 Cree LED. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and the Cree LED logo are CLD-AP37 13 registered trademarks of Cree LED. This document is provided for informational purposes only and is not a warranty or a specification. For product REV 4

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

case temperature (T,) were taken at 700 mA (I,) at an ambient temperature of 20 °C (T,). With these measurements, the power (P), PCB

thermal resistance (8, ,), case to ambient thermal resistance (8,,) and heat sink to ambient thermal resistance (6,. ,) can all be calculated

hs-a

per the following equations.

P=1,*V, (6) Bo = (T, - T,,) /P (7) 8,,= (T.- T.)/P (8) Boe = (Ts 7 T,) 7P (9) Table 6: PCB temperature measurements Board If Vf Power Te Ths Ta Opeb Oca 6hs-a Avg. @ca (A) (v) (W) (°C) (°C) (°c) (c/w) (c/w) (c/w) (c/w) 1 oz. #1 0.700 3.31 2.32 69.64 45.73 22.0 10.32 20.57 10.25 1 oz. #2 0.700 3.26 2.28 70.29 48.03 22.0 9.75 21.16 11.40 1 oz. #3 0.700 3.21 2.24 65.37 44.02 22.0 9.51 19.33 9.81 9.39 19.99 10.60 1oz. #4 0.700 3.22 2.25 66.34 47.65 22.0 8.30 19.69 11.39 oz. #5 0.700 3.25 2.28 65.77 45.15 22.0 9.06 19.23 10.17 202z. #1 0.700 3.32 2.32 71.69 48.19 22.0 10.12 21.41 11.28 2 0z. #2 0.700 3.34 2.34 68.60 45.34 22.0 9.96 19.95 9.99 2 oz. #3 0.700 3.26 2.28 66.95 46.33 22.0 9.04 19.71 10.67 9.61 19.89 10.28 20z. #4 0.700 3.34 2.34 66.36 44.37 22.0 9.39 18.95 9.56 20z. #5 0.700 3.35 2.35 67.57 45.19 22.0 9.54 19.43 9.89 2 oz. filled #1 0.700 3.36 2.35 67.19 44.39 22.0 9.69 19.20 9.51 2 oz. filled #2 0.700 3.33 2.33 67.48 45.11 22.0 9.59 19.51 9.92 2 oz. filled #3 0.700 3.28 2.30 68.06 44.92 22.0 10.08 20.07 9.99 9.65 19.71 10.06 2 oz. filled #4 0.700 3.29 2.30 66.70 44.86 22.0 9.50 19.44 9.94 2 oz. filled #5 0.700 3.37 2.36 70.03 47.87 22.0 9.39 20.35 10.96 4oz. #1 0.700 3.31 2.32 64.35 45.80 22.0 7.99 18.25 10.26 4oz. #2 0.700 3.34 2.33 68.31 48.75 22.0 8.38 19.83 11.46 4 oz. #3 0.700 3.39 2.38 71.87 50.41 22.0 9.03 20.99 11.96 8.40 19.68 11.28 4oz. #4 0.700 3.26 2.28 66.63 47.87 22.0 8.22 19.54 11.32 4o0z. #5 0.700 3.33 2.33 68.12 48.55 22.0 8.40 19.80 11.40 MCPCB #1 0.700 3.36 2.35 63.20 53.20 20.0 4.25 18.37 14.12 MCPCB #2 0.700 3.04 2.13 57.60 50.90 20.0 3.15, 17.67 14.52 MCPCB #3 0.700 3.36 2.35 57.90 50.10 20.0 3.32 16.11 12.80 3.81 17.41 13.60 MCPCB #4 0.700 3.35 2.35 62.00 51.20 20.0 4.61 17.91 13.30 MCPCB #5 0.700 3.37 2.36 60.10 51.30 20.0 3.73 17.00 13.27

© 2010-2023 Cree LED. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and the Cree LED logo are CLD-AP37 1 4 registered trademarks of Cree LED. This document is provided for informational purposes only and is not a warranty or a specification. For product REV 4

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

The results are close to the predicted performance in Chart 2 (which indicates a thermal resistance asymptote of about 3.5 °C/W for an MCPCB) and Chart 7 (which shows a fourteen-via 1.6-mm FR-4 board with a thermal resistance of about 8 °C/W for a 0.254-mm diameter, 2-0z. plated via).’

RECOMMENDED BOARD LAYOUTS

Cree LED recommends creating areas of 10-mil (0.254-mm) vias arranged on a 25-mil (0.635-mm) rectilinear grid. The reason for this choice is the combination of cost, performance and manufacturability. According to several PCB manufacturers, 10-mil holes and 25-mil spacing are reasonable and repeatable production choices when used with a 2-0z. plating solution.

When using multiple LEDs, tighter spacing between emitters results in increased heating. The thermal pads can be connected together and additional copper can be added, if possible.

The following sections illustrate minimum recommended pad sizes for the XT, XP, XB, MX and ML packages.

7 In general, thermal measurement of LEDs is challenging and there are chances for error due to the number of variables involved. Thermocouple placement and subsequent calculations are but two of the concerns. We use these results for their suggestive value rather than their definitive result.

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

FR-4 Boards for XLamp XP and XT LED Packages

| Dashed line represents optional 10-mm thermal pad

—

10, 00

6.00

Figure 15: Recommended footprint for XLamp XP and XT family of LEDs on FR-4 PCB (top and bottom)

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

FR-4 Boards for XLamp XB LED Package

0.635

D0. 254 5x

Figure 16: Minimum footprint for XLamp XB family of LEDs on FR-4 PCB (top and bottom)

© 2010-2023 Cree LED. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and the Cree LED logo registered trademarks of Cree LED. This document is provided for informational purposes only and is not a warranty or a specification. For produ

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

0.635

B0.254 Sr

ptienal 1 pias '

6.00

0,635

D0. 254 Se

Optional 1) vias

Figure 17: Recommended footprint for XLamp XB family of LEDs on FR-4 PCB (top and bottom)

© 2010-2023 Cree LED. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and the Cree LED logo are CLD-AP37 8 registered trademarks of Cree LED. This document is provided for informational purposes only and is not a warranty or a specification. For produ REV 4 1

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

FR-4 Boards for XLamp MX LED Package

| 10,00 |

10, 00

6.00

Figure 18: Recommended footprint for XLamp MX package on FR-4 PCB (top and bottom)

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

FR-4 Boards for XLamp ML LED Package

7.60 6.10 3.30 0

0.254 5

Figure 19: Recommended footprint for XLamp ML package on FR-4 PCB (top and bottom)

specifications, please see the data sheets available at www.cree-led.com

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OPTIMIZING PCB THERMAL PERFORMANCE

CHEMICAL COMPATIBILITY

It is important to verify chemical compatibility when selecting the interface materials to use between the board and the heat sink, as well as other materials to which the LEDs can be exposed. Certain materials from FR-4 board fabrication and assembly processes, e.g., adhesives, solder mask and flux residue, can outgas and react adversely with the materials in the LED package, especially at high temperatures when a non-vented secondary optic is used. This interaction can cause performance degradation and product failure. Each family or individual LED product has an application note identifying substances known to be harmful to XLamp LEDs.'° Consult your PCB manufacturer to determine which materials it uses.

REFERENCES

Electronics Cooling, September 1997, Vol.3, No.3, “Calculation Corner: One-dimensional heat flow” Bruce M. Guenin, Ph.D., Associate Editor

Electronics Cooling, May 1998, Vol.4, No.2, “Calculation Corner: Conduction heat transfer in a printed circuit board” Bruce M. Guenin, Ph.D., Associate Editor

Electronics Cooling, August 2004, Volume 10, Number 3, “Calculation Corner: Thermal Vias — A Packaging Engineer's Best Friend”, Bruce M. Guenin, Ph.D., Associate Editor

“Thermal and High Current Multilayer Printed Circuit Boards With Thermagon T-lam and Hybrid Boards” January 31, 2001, Thermagon, Inc., Courtney R. Furnival

“Thermal Considerations for QFN Packaged Integrated Circuits” AN315 rev 1, July 2007, Cirrus Logic, Inc.

10 XT Family LEDs Soldering & Handling XP Family LEDs Soldering & Handling XB Family LEDs Soldering & Handling MX Family LEDs Soldering & Handling ML Family LEDs Soldering & Handling

specifications, please see the data sheets available at www.cree-led.com

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