ICEZUM
Alhambra rie
I FPGA e++e ADC
uss ote — iCEAOHXIK ADs7924 (G@==mpe-—_-e ME Power —_ FTDI SPL MGND f Serial Pin MV Analog Pin (control © 6-17v A recaceio (sv) MED Physical Pin Input pins: at least +/-2mA . driving strength required [BY cestudio name ca (0) cing srngth reute 4K (steady state) 40R (Transitions) 2.1mm = FPGA Direct GPIO (3V3) === oO Absolute Max per pin 8mA. 3V3 Pins Recommended 6 mA
RST) Reset ' — — BB clock : a “El (1.57 |(B04)/ SDA = saag) (CLE) Clock Enable | he a eee call TUTTI & ee < = Cm) (CLK |\Clock 12Mhz EX) 37A/ 3 . @e 8 ee 3 ee 2 ee g <a s ee ee 8 ee g ee g @e 3 ee g Cm) & 5V REF AR Fi ee °®@ (interrupt) E=}\ 1.60 |/ADC_INT) SV Pins ps) (SDA /758 /ADCISDA) 12¢ eee ane SCL /Ei/159 [ADC SCL) Ad Connected to ADS7924 via 2 f — (SK |G] 246) SCR maa pon ; Tou abbe 2) A) = |=_= 0! A Analog Reference AREF >= 3V3. t e t FTDI
ae YT} o . qog Max 3A for all power supply pins Made with
(00 3 ER 1A\/DCD) Inkscape Aes NOV 2017
ver 1.1 rev2