HDLab - FPGA Development Board
: 8 z g
AlL Al
ala
Ed
7 Segment
AN ANI ANI ANO icc ea
MMi Lt. Lt Ld.
Bab ch ah ob ck ch ol CACBCCCDCE CF CG DP
cc DP ‘ANO ANL ‘ANZ ‘AN3
cA cB cc
SPARTAN-6
co cE cr
STAG PORT
BUZZER eu
N/c N/c
ep Tex CLK som-cik > GSE eeeseede eeeeceees =BHEEE- = EHH 000000000 0000000000 E.) seeeeaes eeebeeee
Power = BB cn controt. (ID Physicatpin (7) AnatogPin Pin Name @ Digital Pin