ky
USBLC6-4SC6Y
Automotive very low capacitance ESD protection
Features
4 data-line protection
Protects Vays
Very low capacitance: 3 pF Very low leakage current: 10 nA SOT23-6L package
RoHS compliant
AEC Q101 qualified
Benefits
m Very low capacitance between lines to GND for optimized data integrity and speed
m Low PCB space consumption, 9 mm? maximum foot print
m Enhanced ESD protection: IS010605 up to 25 kV guaranteed at device level
ESD protection of Vays
High reliability offered by monolithic integration
Fast response time
Consistent D+ / D- signal balance:
— Very low capacitance matching tolerance I/O to GND = 0.015 pF
— Compliant with USB 2.0 requirements
Complies with the following standards m 1S010605, C = 150 pF, R= 330 — 25 kV (air discharge) — 15 kV (contact discharge) m 1S010605, C = 330 pF, R = 330 — 15 kV (air discharge) — 15 kV (contact discharge) mg ISO 7637-3 — Pulse 3a: Vs = -150 V — Pulse 3b: Vs = +100 V
TM: Transil is a trademark of STMicroelectronics
September 2012
Datasheet — production data
SOT23-6L USBLC6-4SC6Y(JEDEC MO178AB)
Figure 1. Functional diagram @ voi [4] |6] vo4 GND | 2 | 15 | Veus vo2 | 4] vos Applications
USB 2.0 ports up to 480 Mb/s (high speed) Compatible with USB 1.1 low and full speed High-speed data lines in smart junction boxes Ethernet port: 10/100 Mb/s
Video line protection
Description
The USBLC6-4SCE6Y is a monolithic device dedicated to ESD protection of high speed interfaces, such as USB 2.0, Ethernet links and video lines.
Its very low line capacitance secures a high level of signal integrity without compromising in protecting sensitive chips against the most stringent characterized ESD strikes.
Doc ID 023199 Rev 2 1/10
This is information on a product in full production.
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Characteristics
USBLC6-4SC6Y
Note:
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Characteristics
Table 1.
Absolute maximum ratings (tamp = 25 °C) - Generic parameters
Symbol
Parameter
1SO10605 (C = 330 pF, R = 330 Q):
Value
Unit
air discharge 15 contact discharge 15 Vv Peak pul lt kV Pp Peak pulse vouage ISO10605 (C = 150 pF, R = 330 9): air discharge 25 contact discharge 15 Tstg _ | Storage temperature range -55 to +150 °c Tj Operating junction temperature range -40 to +150 °C TL Lead solder temperature (10 seconds duration) 260 °C
Figure 2.
Electrical characteristics (definitions)
For a surge greater than the maximum values, the diode will fail in short-circuit.
Symbol Parameter Ver Breakdown voltage law Leakage current @ V,,
Vem Stand-off voltage lop Peak pulse current Cine Line capacitance
}) Slope:1/Ry
pp
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USBLC6-4SC6Y
Characteristics
Table 2. Electrical characteristics (Tamp = 25 °C) Value Symbol Parameter Test Conditions Unit Min. Typ. Max. IRM Leakage current Vram = 9.25 V 10 150 nA Ver Breakdown voltage between Vays and Ig= 1 mA 6 v GND Ve Forward voltage I-F=10 mA 0.86 Vv Ipp = 1A, 8/20 ps 12 Vv Any I/O pin to GND V Clamping voltage cL Ipp = 5 A, 8/20 ps 47 V Any I/O pin to GND Cifo-GND_ | Capacitance between I/O and GND VR = 1.65 V 3 4 pF ACi/o-GND 0.015 Cijo-io | Capacitance between I/O VR = 1.65 V 1.85 27 pF ACi/o-i/0 0.04 Figure 3. Capacitance versus voltage Figure 4. _ Line capacitance versus frequency (typical values) (typical values) C(pF) C(pF) 5.0 5.0 TTT 4.0 = 4.0 — 35 3.5 to FT donid.end - Vea. 68 25 25 20 pups 20 15 1.5 1.0 1.0 os Data line voltage (V) 05 F(MHz) 00 poe oo aaa 0.0 Os 1.0 15 2.0 25 3.0 35 4.0 45 5.0 1 10 100 1000 Figure 5. Relative variation of leakage Figure 6. Frequency response current versus junction temperature (typical values) InM[Tj] / IRu[Tj=25°C] $21(dB) 100 10
Vaus=5V
-5.00
-10.00:
-15.00;
T(°C)
-20.00:
F(Hz)
25
50 75 100 125
100.0k 1.0M
10.0M 100.0M
1.0G
4|
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Application and design guidelines USBLC6-4SC6Y
Figure 7. ESD response to ISO10605, Figure 8. ESD response to ISO10605, C= 150 pF, R = 330 © (+15 kV air C = 150 pF, R = 330 Q (-15 kV air discharge) discharge)
~ ee i
Figure 9. Analog crosstalk results 0.00
dB
- 30.00
- 60.00 pe
| Vaal
- 90.00
F (Hz)
- 120.00 LU
100.0k 1.0M 10.0M fHz 100.0M 1.0G
2 Application and design guidelines
More information is available in the STMicroelectronics Application note AN2689, “Protection of automotive electronics from electrical hazards, guidelines for design and component selection”.
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USBLC6-4SC6Y
Ordering information scheme
3 Ordering information scheme
Figure 10. Ordering information scheme
USB LC 6-4 SC6 Y
Product designation
Low capacitance
Breakdown voltage
6=6.1V
Number of lines protected 4=4 lines
Package
SC6 = SOT23-6L Automotive grade
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Package information USBLC6-4SC6Y
4
6/10
Package information
@ Epoxy meets UL94, VO
e@ Lead-free package
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
Table 3. SOT23-6L dimensions
Dimensions
Ref. Millimeters Inches
Min. | Typ. | Max. | Min. | Typ. | Max. Al 0 0.15] 0 0.006 A2 | 0.90 1.30 | 0.035 0.051 b | 0.30 0.50 | 0.012 0.02 Cc | 0.09 0.20 | 0.004 0.008 D | 2.80 3.05 | 0.110 0.120 E | 1.50 1.75 | 0.059 0.069 e 0.95 0.037 H | 2.60 3.00 | 0.102 0.118 L | 0.30 0.60 | 0.012 0.024 0 o° 10° | O° 10°
Figure 11. SOT23-6L footprint (mm)
an
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USBLC6-4SC6Y Recommendation on PCB assembly
5 Recommendation on PCB assembly
5.1 Solder paste
1. Use halide-free flux, qualification ROLO according to ANSI/J-STD-004.
2. “No clean” solder paste recommended.
3. Offers a high tack force to resist component displacement during PCB movement. 4. Use solder paste with fine particles: powder particle size 20-45 pm.
5.2 Placement
1. Manual positioning is not recommended.
2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering.
3. Standard tolerance of + 0.05 mm is recommended.
4. 3.5N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages.
5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool.
6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
5.3 PCB design preference 1. Tocontrol the solder paste amount, the closed via is recommended instead of open vias.
2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
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Recommendation on PCB assembly USBLC6-4SC6Y
5.4 Reflow profile
Figure 12. ST ECOPACK® recommended soldering reflow profile for PCB mounting
A 240-245 °C] Temperature (°C) 240-245 c 250 Z -2 °C/s 2-3°C/s 200 60 sec (90 max) L3 °C/s at 150 -6 °C/s 100 f 0.9 °C/s 50 Time (s) ty) go 6080120180 ~180~«210~«ado aa Note: Minimize air convection currents in the reflow oven to avoid component movement.
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USBLC6-4SC6Y
Ordering information
6
4|
Ordering information
Table 4. Ordering information Order code Marking Package Weight Base qty Delivery mode
USBLC6-4SC6Y UL4Y SOT23-6L 16.7 mg 3000 Tape and reel Revision history Table 5. Document revision history
Date Revision Changes 14-May-2012 1 First issue. 06-Sep-2012 2 Updated dimensions A1 max, b min., and L min. in Table 3.
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USBLC6-4SC6Y
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